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december 2014 docid027308 rev 1 1 / 15 this is information on a product in full production. www.st.com std15n60m2 - ep n - channel 600 v, 0.340 typ., 11 a mdmesh? m2 ep power mosfet in a dpak package datasheet - production data figure 1 : internal schematic diagram features order code v ds @ t jmax r ds(on) max. i d std15n60m2 - ep 650 v 0.378 11 a ? extremely low gate charge ? excellent output capacitance (c oss ) profile ? very low turn - off switching losses ? 100% avalanche tested ? zener - protected applications ? switching applications ? tailored for very high frequency converters (f > 150 khz) description this device is an n - channel power mosfet developed using mdmesh? m2 ep enhanced performance technology. thanks to its strip layout and an improved vertical structure, the de vice exhibits low on - resistance, optimized switching characteristics with very low turn - off switching losses, rendering it suitable for the most demanding very high frequency converters. table 1: device summary order code marking package packaging std15n60m2 - ep 15n60m2ep dpak tube dpak d(2, t ab) g(1) s(3) am01476v1_tab
contents std15n60m2 - ep 2 / 15 do cid027308 rev 1 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical charac teristics ................................ ................................ 4 2.1 electrical characteristics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package mechanical data ................................ ............................. 10 4.1 dpak (to - 252) type a ................................ ................................ .... 11 5 revision history ................................ ................................ ............ 14
std15n60m2 - ep electrical ratings docid027308 rev 1 3 / 15 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d drain current (continuous) at t c = 25 c 11 a i d drain current (continuous) at t c = 100 c 7 a i dm (1) drain current (pulsed) 44 a p tot total dissipation at t c = 25 c 110 w dv/dt (2) peak diode recovery voltage slope 15 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature notes: (1) pulse width limited by safe operating area. (2) i sd 11 a, di/dt 400 a/s; v ds peak < v (br)dss , v dd = 400 v. (3) v ds 480 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max 1.14 c/w r thj - pcb (1) thermal resistance junction - pcb max 50 c/w notes: (1) when mounted on fr - 4 board of 1 inch2, 2 oz cu table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetetive or not repetetive (pulse width limited by t jmax ) 2.8 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar ; v dd = 50 v) 125 mj
electrical characteristics std15n60m2 - ep 4 / 15 docid027308 rev 1 2 electrical characteristics t c = 25 c unless otherwise specified table 5: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0 v, v ds = 600 v 1 a v gs = 0 v, v ds = 600 v, t c = 125 c 100 a i gss gate - body leakage current v ds = 0 v, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 5.5 a 0.340 0.378 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 590 - pf c oss output capacitance - 30 - pf c rss reverse transfer capacitance - 1.1 - pf c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 v - 148 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 7 - q g total gate charge v dd = 480 v, i d = 11 a, v gs = 10 v (see figure 15: "gate charge test circuit" ) - 17 - nc q gs gate - source charge - 3.1 - nc q gd gate - drain charge - 7.3 - nc notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss table 7: switching energy symbol parameter test conditions min. typ. max. unit e (off) turn - off energy (from 90% v gs to 0% i d ) v dd = 400 v, i d = 1.5 a r g = 4.7 ?, v gs = 10 v - 4.7 - j v dd = 400 v, i d = 3.5 a r g = 4.7 ?, v gs = 10 v - 5.2 - j
std15n60m2 - ep electrical characteristics docid027308 rev 1 5 / 15 table 8: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 5.5 a r g = 4.7 , v gs = 10 v (see figure 14: "switching times test circuit for resistive load" and figure 19: "switching time waveform" ) - 11 - ns t r rise time - 10 - ns t d(off) turn - off - delay time - 40 - ns t f fall time - 15 - ns table 9: source drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 11 a i sdm (1) source - drain current (pulsed) - 44 a v sd (2) forward on voltage v gs = 0 v, i sd = 11 a - 1.6 v t rr reverse recovery time i sd = 11 a, di/dt = 100 a/s, v dd = 60 v (see figure 16: " test circuit for inductive load switching and diode recovery times" ) - 280 ns q rr reverse recovery charge - 2.7 c i rrm reverse recovery current - 19.5 a t rr reverse recovery time i sd = 11 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 16: " test circuit for inductive load switching and diode recovery times" ) - 400 ns q rr reverse recovery charge - 3.8 c i rrm reverse recovery current - 19 a notes: (1) pulse width is limited by safe operating area (2) pulsed: pulse duration = 300 s, duty cycle 1.5%
electrical characteristics std15n60m2 - ep 6 / 15 docid027308 rev 1 2.2 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : ou tput characteristics figure 5 : transfer characteristics figure 6 : normalized gate threshold voltage vs temperature figure 7 : normalized v (br)dss vs. temperature gipg121220141416m t i d 15 5 0 0 4 v ds (v) 8 (a) 12 6v v gs =7, 8, 9, 10v 10 20 16 4v 5v gipg121220141419m t i d 20 10 0 0 4 v gs (v) 8 (a) 2 6 5 15 v ds =17v 0.9 0.8 0.7 0.6 -75 -25 t j (c) 1.0 25 75 125 i d = 250 a 1.1 v gs(th) (norm) gipg18 1 120141615als gipg19 1 120141457als -75 t j (c) -25 75 25 125 0.88 0.92 0.96 1.04 1.00 1.08 i d = 1m a v (br)dss (norm) i d 10 1 0.1 1 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 10s 1ms 100s 0.1 tj=150c t c=25c single pulse 10ms 100 gipg1612201415 1 1m t 0.05 0.01 0.1 0.2 0.02
std15n60m2 - ep electrical characteristics docid027308 rev 1 7 / 15 figure 8 : static drain - source on - resistance figure 9 : normalized on - resistance vs temperature figure 10 : gate charge vs. gate - source voltage figure 11 : capacitance variations figure 12 : turn - off switching loss vs drain current figure 13 : source - drain diode forward characteristic gipg121220141431m t r ds(on) 0.330 0.320 0 2 i d (a) ( ) 0.340 v gs =10v 4 0.350 8 6 0.360 10 1.4 1.0 0.6 0.2 -75 t j (c) -25 75 25 125 1.8 2.2 v gs = 10 v r ds(on) (norm) gipg18 1 120141628als gipg121220141425m t v gs 6 4 2 0 0 8 q g (nc) (v) 8 12 10 v dd =480v i d = 1 1 a 12 100 0 200 v ds 4 v ds (v) 300 400 16 500 600 c 1000 10 1 0.1 0.1 10 v ds (v) (pf) 1 100 ciss coss crss 100 gipg121220141441m t gipg121220141453m t e o f f 4.4 0.5 1 i d (a) (j) 2.5 1.5 2 3 4.6 4.8 5 5.2 5.4 3.5 v dd =400 v , r g =4,7,v gs =10v gipg161220141014m t v sd 0 4 i sd (a) (v) 2 10 6 8 0.5 0.6 0.7 t j =-50c t j =150c t j =25c 0.8 0.9 1 1.1
test circuits std15n60m2 - ep 8 / 15 docid027308 rev 1 3 test circuits figure 14 : switching times test circuit for resistive load figure 15 : gate charge test circuit figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit am01469v 1 v dd 47 k 1 k 47 k 2.7 k 1 k 12 v v i v gs 2200 f p w i g = const 100 100 nf d.u.t. v g
std15n60m2 - ep test circuits docid027308 rev 1 9 / 15 figure 18 : unclamped inductive waveform figure 19 : switching time waveform v (br)dss v dd v dd v d i dm i d am01472v 1 am01473v 1 0 v gs 90% v ds t on 90% 10% 90% 10% t d(on) t r t t d(off) t f 10% 0 off
package mechanical data std15n60m2 - ep 10 / 15 docid027308 rev 1 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
std15n60m2 - ep package mechanical data docid027308 rev 1 11 / 15 4.1 dpak (to - 252) type a figure 20 : dpak (to - 252) type a package outline 0068772_r
package mechanical data std15n60m2 - ep 12 / 15 docid027308 rev 1 table 10: dpak (to - 252) type a mechanical data dim. mm min. typ. max. a 2.20 2.40 a1 0.90 1.10 a2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 d 6.00 6.20 d1 5.10 e 6.40 6.60 e1 4.70 e 2.28 e1 4.40 4.60 h 9.35 10.10 l 1.00 1.50 l1 2.80 l2 0.80 l4 0.60 1.00 r 0.20 v2 0 8
std15n60m2 - ep package mechanical data docid027308 rev 1 13 / 15 figure 21 : dpak (to - 252) type a recommended footprint all dimensions are in mm fp0068772_r
revision history std15n60m2 - ep 14 / 15 docid027308 rev 1 5 revision history table 11: document revision history date revision changes 16 - dec - 2014 1 first release.
std15n60m2 - ep docid027308 rev 1 15 / 15 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics C all rights reserved

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